In recent years, low cost, high speed, and high capacity storage devices are being demanded. Accordingly, in some of recent storage devices, a system configuration for connecting a plurality of semiconductor memories to a memory bus and a circuit configuration for placing an on-chip input termination resistor circuit on the semiconductor memory have been employed. It is to be noted that the on-chip input termination resistor circuit is also referred to as an ODT (On Die Termination) circuit or an OCT (On Chip Termination) circuit. In the following description, the term “ODT circuit” will be used.
The ODT circuit is a circuit placed for the purpose of matching the impedance on the side of semiconductor memories with the characteristic impedance on the side of the substrate interconnection to secure waveform quality. However, a resister element (at 50 ohms, in general) matched with the characteristic impedance of the substrate interconnection is connected in series between a power source and a ground (GND). Accordingly, direct-current (DC) electricity constantly flows between the power source and the ground (GND), which causes a problem of increased power consumption in the semiconductor memories. The increased power consumption in the semiconductor memories also causes increased power consumption in the entire signal transmission system. In the case where the semiconductor memory is a flash memory in particular, the increased power consumption results in higher chip temperature, which leads to a larger leakage current and a shorter data retention period (retention period). This causes a problem of a shortened life span of the flash memory.